The present invention relates to testing techniques for semiconductor integrated circuits, in particular, for large-scale integrated circuits (LSIs).
Various techniques of a scan testing and a direct-access testing for LSIs are described in "Designer's Guide to Testable ASIC Devices" by W. M. Needham (Ch. 5, pp. 87-124, Van Nostrand Reinhold. N.Y. 1991). The testing techniques for LSIs are desired to meet various requirements as follows: All the blocks and signal paths included therein can be tested in a short period of time: an additional circuit for the test is small; the number of additional wires for the test is small: and the operation speed of the tested circuit is not largely decreased in the normal mode.
It is herein assumed that one block contained in an LSI includes a combinational logic circuit and a plurality of flip-flops. The plural flip-flops are embedded on signal paths in the combinational logic circuit, so as to latch corresponding signals in the combinational logic circuit during the normal mode operation of the LSI. In a scan mode of the scan testing technique, these flip-flops are cascaded to one another so as to form a scan chain (shift register). An input signal for the scan testing, which is supplied from the outside of the LSI bit by bit in a serial manner in the scan mode, is latched by the shift register, and the latched signal is then supplied to the combinational logic circuit. Each flip-flop can fetch the test result of the combinational logic circuit in the normal mode. The test result thus fetched by the flip-flops is output bit by bit in a serial manner from the shift register to be observed in the external of the LSI.
When one LSI includes a plurality of blocks, it is desirable that each block can be tested independently from one another for performing the test efficiently. According to the scan testing technique, a plurality of flip-flops are additionally provided in the periphery (on the sides of the input port and the output port) of each of the plural blocks, and all the flip-flops are wired to one another so as to form one scan chain. According to the direct-access testing technique, a plurality of multiplexers are additionally provided and wired to one another so that a test input can be directly set in each block from the outside and that the test result of each block can be directly observed on the outside.
According to the scan testing technique utilizing a plurality of flip-flops embedded on signal paths in a combinational logic circuit, in the case where the block to be tested includes two types of flip-flops, one of which is a positive edge triggered type that is operated synchronously with the rising edge of a clock signal and the other of which is a negative edge triggered type that is operated synchronously with the falling edge of a clock signal, there arises a problem that there is a possibility that a test signal cannot be correctly scanned in. Japanese Laid-Open Patent Publication No. 2-218974 discloses a technique for overcoming this problem, in which a scan chain is formed so that all the negative edge triggered flip-flops are followed by all the positive edge triggered flip-flops. This technique, however, leads to another problem that the constructing freedom of a scan chain is largely degraded.
The scan testing technique used for an LSI including a plurality of blocks in which a scan chain is additionally provided in the periphery of all the blocks is advantageous in the small number of additional wires for the test. However, since setting of a test input and the observation of a test result can be performed bit by bit, a long period of time is required for the test. Furthermore, this technique has other problems that an additional circuit for the test is large and that the operation speed in the normal mode is largely decreased.
The direct-access testing technique for an LSI including a plurality of blocks is advantageous in that the time required for the test can be shorten because setting of a test input and the observation of a test result can be performed with regard to a plurality of bits at a stroke. However, this technique has a problem that a large number of wires are additionally provided for the test.